1. Field of the Invention
The present invention relates to a semiconductor memory device and a process for producing it. More particularly, the invention relates to a semiconductor memory device of mask ROM (read only memory) as so-called as a planer cell structure, and to a production process thereof.
2. Description of the Related Art
A common MOS (metal-oxide semiconductor) type semiconductor integrated circuit device is formed such that field oxide separates elements and that an impurity is introduced into a substrate in the self alignment technique with gate electrodes as a mask to form source and drain regions. Such a circuit device requires one or two contacts of the source and drain regions for one transistor, so that contact margins and a wiring pitch may affect a degree of integration in circuit. To avoid that, there is a semiconductor integrated circuit device as so-called as a planer cell structure proposed for example in Japanese Patent Application Laying Open (KOKAI) Nos. 61-288464 and 63-96953.
FIGS. 1 and 2 show the planer cell structure. In the planer cell structure, continuous diffused regions 2s for source regions of memory transistor and continuous diffused regions 2d for drain regions of memory transistor are formed in parallel with each other on a substrate 1, and word lines (gate electrodes) 4 are formed to cross the both diffused regions 2s and 2d with an insulating layer 3 intervening between them on the substrate 1. The planer cell structure needs no field oxide for element separation. Further, a plurality of memory transistors share a source region 2s and a drain region 2d. Thus, a contact is enough for several to several ten's memory transistors, which is advantageous for high integration design. A size of memory cell in the planer cell structure is determined by a pitch of the diffused regions 2s, 2d for the source and drain regions, and by a pitch of the word lines 4.
There are needs in the market for more high density and integration not only in semiconductor memory devices but also in all semiconductor integrated circuit devices. To make a memory cell array of planer cell structure finer, it is necessary to reduce the pitches of the diffused regions 2s, 2d and of the words lines 4. The pitches depend upon the performance of processing apparatuses. The smallest pitch is 2 .mu.m with the processing apparatuses presently available in mass production level.
If a finer planer cell structure should be sought for, the short channel effect restricts the reduction in pitch in the diffused layers 2s, 2d. The short channel effect may be avoided by employing diffused layers of LDD (lightly doped drain) structure in common MOS transistors such as a peripheral transistor. The planer cell structure cannot be, however, suitable for use of the LDD structure because of the structural limitations thereof.